When carbon nanotubes are contacted ohmically and local depletion regions are formed, we observe a stepwise increase in device conductance in units of e2/h up to a maximum of ~4e2/h. The appearance of steps as a function of gate voltage in units of the nondegenerate quantum of conductance, e2/h, suggests that at zero external field both the spin and band degneracies present in carbon nanotubes may be lifted. This result is quite surprising, and may permit the fabrication of future devices which include intratube spin filters.
Fig. 1 (a) Differential conductance G = dI/dV as a function of source drain bias, VSD, and side gate voltage, VSG, for a bent nanotube device at temperature T = 29 K. The series resistance subtracted from the data is indicated. Traces are taken at fixed VSG; bunched traces correspond to conductance plateaus. Four plateau-like features are evident around VSD = 0, the lowest around 0.2e2/h. A dip in conductance appears around VSD = 0. Away from VSD = 0, half-plateaus appear near odd half-integer multiples of e2/h. Red and blue lines show where data shown in (b) are taken. (b) Slices from (a) at fixed VSD for low bias (red) and high bias (blue) as a function of VSG for fixed values of VSD. The high-bias trace is offset by 2 V in VSG for clarity. Inset: AFM topographic image of the device, showing a side gate (top right), and a tube that has been pushed towards the gate. Total device length is ~1.5mm. (c) G as a function of VSD and VSG at 4 K for the same device with VSG set below the first plateau. Coulomb blockade diamonds are evident, with peak spacing ~0.05 V in VSG. Typical excited state level spacings, DE, are 2-3 meV, corresponding to a device length L ~ 500-700 nm. (d) G as a function of VSD and VSG at 4 K in the high conductance region (G > e2/h). The observed pattern is consistent with Fabry-Perot interference. The typical periodicity of the interference fringes, DVSG ~ 0.3 V, is marked on the figure. High conductance peaks in the interference pattern are suppressed at higher temperatures as in (a). For this panel, RS=1.2 kW.
Fig. 2 (a) Transconductance, dG/dVSG, as a function of VSD and VSG, for the data set in Fig. 1a. Dark regions correspond to plateaus, bright regions to transitions between plateaus. Blue lines are guides to the eye showing the evolution of conductance modes with VSD and VSG. (b-d) Models for transconductance evolution with gate voltage for a four-mode 1D conductor for the case of (b) four-fold degeneracy, (c) two-fold degeneracy, (d) fully broken degeneracy. Numbers denote expected conductance values for plateaus, in units of e2/h (see text for discussion). Note the experimental data most resembles scenario (d).
Fig. 3 (a) Differential conductance G as a function of gate voltage for an un-bent nanotube with top gates, measured at finite bias. Four half-plateaus spaced by ~ e2/h are visible. A background resistance of 34.2 kW is subtracted, determined by setting the high-bias saturating conductance to ~ 4e2/h. Upper Inset: SEM of a device similar to the one measured. The nanotube is embedded in SiO2 and top gates are patterned using ebeam lithography. Arrows show the location of the tube. Lower Inset: G as a function of the two top gates, taken at VSD = 35 mV. The appearance of a sharp corner and a square pattern indicates independent localized gating effect. Note that conductance saturates near 4e2/h for high negative gate voltages. (b) G as a function of backgate voltage, VBG, at VSD = 35 mV. Conductance plateaus appear for both positive and negative gate voltages with a gapped region in between, indicating transport through holes (blue trace, bottom axis) or electrons (red trace, top axis). Different series resistances have been subtracted from the traces as noted on the figure. The origins of the asymmetries in series resistances as well as in the relevant gate voltage scales for the two branches are not known. (c) G as a function of VSD and top gate voltage at T = 50 K for a bent-tube device with a top-gate. Series resistance of 11.8 kW has been subtracted. Plateaus spaced by ~ e2/h appear around VSD = 0 and half-plateaus appear at higher bias.
Fig. 4 (a) Temperature dependence of conductance plateaus around VSD = 0, from T = 4 K to 50 K (red to black), for the device in Fig. 1b (inset). Note that the plateau near e2/h rises with temperature while that near 2e2/h does not. (b) Evolution of the low-bias conductance plateaus for the same device (different cooldown) in a magnetic field perpendicular to the sample plane with VBG = 0.68 V and VSD = 2 mV. No Zeeman splitting of plateaus is observed up to B = 8 T. Curves are offset in VSG for clarity. No series resistance is subtracted in (a) or (b).
For more information contact Michael Biercuk (biercuk@fas)